Process Preparation for PCB Assembly and Test
Process Preparation (formerly known as vPlan) software by Valor. It is a complete engineering solution for DFx, process development and test engineering for PCB assembly operations. It improves the efficiency and quality of PCB assembly with tools such as optimized front-end DFA analysis, BOM validation, stencil design, SMT programming and line balancing.
Data Preparation sub-module supports a wide set of CAD and CAM data formats to create PCA data. Featuring: Complex BOM file support, a central master vendor part library (VPL), test, and inspection processes, common product data model and a highly streamlined, repeatable work flow.
DFA Analysis consists of a group of manufacturing-focused checks that cover external fabrication and assembly analysis for both single PCB and PCB panels.
SMT programming sub-module is a complete SMT programming solution for all supported machine models, including: part data models, Virtual Sticky Tape, offline process simulation, auto-generation option and a multi-vendor line.
Documentation sub-module creates clear work instructions for assembly processes. It eliminates production process errors by synchronizing each SMT, THT and hand-assembly process to its corresponding work instruction, and automatically updates. Documents can be output as read-only PDF sets, or as an interactive document viewed through the Valor Document Viewer.
Stencil Design sub-module optimizes stencil design, reduces errors and shortens the review cycle between the manufacturer and the stencil supplier.
It uses the same common datasets as other Valor processes, ensuring a streamlined, error-free workflow. In addition to creating the paste stencil, it will also save the design to ODB++ or RS-274X Gerber files.
Use the Inspection Programming sub-module to create machine-specific automated optical inspection (AOI) and automated optical x-ray inspection (AXI) output files on supported platforms.
It optimizes the product data model and MPL during the DFx analysis, to support test and inspection programming.
Create machine-specific ICT and FPT output files for supported platforms including physical design for test (DFT) analysis.
The optional fixture reuse feature performs automated analysis of fixture files on new revisions of a PCB, determining which test probes can be altered.